Efficient Resource-Aware Neural Architecture Search with a Neuro-Symbolic Approach

The challenge of classification confidence estimation in dynamically-adaptive neural networks

Exploring Software Models for the Resilience Analysis of Deep Learning Accelerators: the NVDLA Case Study

A Boolean model for delay fault testing of emerging digital technologies based on ambipolar devices

A Built-In Self-Testing Framework for Asynchronous Bundled-Data NoC Switches Resilient to Delay Variations

Power efficiency of switch architecture extensions for fault tolerant NoC design

Exploiting Network-on-Chip Structural Redundancy for A Cooperative and Scalable Built-In Self-Test Architecture

System-Level Infrastructure for Boot-time Testing and Configuration of Networks-on-Chip with Programmable Routing Logic

High quality test vectors for bridging faults in the presence of IC's parameters variations

Delay fault detection problems in circuits featuring a low combinational depth

Pulse propagation for the detection of small delay defects

"Victim gate" crosstalk fault model

Annotated bit flip fault model

An evolutionary approach to the design of on chip pseudorandom test generators

Problems due to open faults in the interconnections of self-checking data-paths

Self-checking scheme for the on-line testing of power supply noise

Optimization of error detecting codes for the detection of crosstalk originated errors

Test pattern generation for iddq: increasing test quality

Correlation between IDDQ Testing Quality and Sensor Accuracy